Field of Invention
The present invention relates to systems and methods for substrate processing, and more particularly to a poly-phased inductively coupled plasma source.
Description of Related Art
Scaling is a primary concern in semiconductor processing, both at the device level, and at the wafer level. At the device level, there is a constant drive to reduce the size or physical dimensions of features formed on or in the surface of the wafer. At the wafer level, on the other hand, there is a constant drive to increase the overall wafer size, so that more devices or features can be formed in a single set of process steps. Increased wafer size reduces overall device processing costs and efficiency.
Ideally, device consistency is improved with larger wafer size as well, but that may not always be the case, due to limitations of existing semiconductor fabrication tools. For example, a typical plasma source of an Ionized Physical Vapor Deposition (IPVD) system is generally not capable of providing a sufficiently uniform plasma field when used on wafers over 300 mm in size. In particular, uniformity is a substantial problem when the wafer size approached 450 mm, especially when system requirements dictate that the source non-uniformity be below 3%, as is typically the case.
Scaling and development of 450 mm capable IPVD represents a new level of complexity. Prior hardware solutions that include geometric scaling and operation modes to meet process requirements have been found to be either insufficient or too costly to implement when scaled toward 450 mm, particularly in applications where the IPVD is used to deposit barrier and seed layers into trenches and vias that form interconnects for Integrated Circuits (ICs). Although 300 mm IPVD tools have been previously developed, the 300 mm IPVD systems utilize a high-density plasma source inductively coupled plasma (ICP) with three-dimensional (3D) antennas. To scale such tools into 450 mm is difficult by mechanistic increase of dimensions, if not impossible, due to unknown optimal configuration and interplay of several sources inside the vacuum chamber. Such systems typically include three sub-sources: a metal source, a high density plasma source, and a substrate bias source.
In contrast to the “scaling up” of the individual components for IPVD source to adjust the tool to increased wafer size, the metallization features on the wafer are “scaled down” to follow trend that is generally referred in semiconductor fabrication as “Moore's law”. Unfortunately, the physics of the plasma, such as interactions between electrons and atoms, is not scaled accordingly, and plasma has to be generated and sustained such that tradeoffs of both scaling challenges are balanced. There is a challenge to generate such a large plasma field, specifically plasma consisting of metal atoms and ions, and still meet process performance at the wafer surface, which may be 20 nm to 14 nm per node. At this metalization scale the critical dimensions of features for barrier and seed deposition are in the range of 32 nm to 12 nm. Another challenge is to provide system with high throughput but low cost of operation, which is still suitable for technology transition into 450 mm ranges at a mass fabrication level.